The present disclosure relates to a semiconductor memory device, and more particularly to a delay locked loop (DLL) circuit.
In general, a semiconductor memory device has been continuously developed to improve an operation speed and an integration degree. Particularly, in order to increase the operation speed of the semiconductor memory device, a synchronous memory device capable of being synchronized with an external clock signal of a memory chip has recently been developed.
The above-mentioned semiconductor memory device generally uses a delay locked loop (DLL) for generating an internal clock signal acquired when an external clock signal is delayed by a predetermined period of time so that data can be correctly synchronized with a rising edge and a falling edge of the clock signal.
As described above, the delay locked loop (DLL) generates the internal clock signal in which an internal delay factor of a DRAM is compensated for the external clock signal. This above-mentioned condition is referred to as a “locking status”. This locking status is indicative of a specific condition in which a reference clock signal (refclk) is synchronized with a feedback clock signal (fbclk). In this case, the conventional delay locked loop (DLL) can allow the feedback clock signal (fbclk) to be synchronized with the reference clock signal (refclk).
FIG. 1 is a block diagram illustrating a conventional delay locked loop (DLL).
Referring to FIG. 1, the conventional delay locked loop (DLL) buffers an external clock signal (CLK) via clock receiver 101, and outputs a reference clock signal (refclk). Delay line 102 delays the reference clock signal (refclk) generated from the clock receiver 10 by a predetermined period of time, and outputs the delayed reference clock signal. In this case, the delay line 102 receives a control signal of phase detector 105, and variably increases/reduces the delay period.
Internal delay 104 delays the signal received from the delay line 102 by a predetermined period of time, and outputs a feedback clock signal (fbclk).
In this case, the internal delay 104 includes a predetermined delay period acquired by modeling a first delay factor and a second delay factor. The first delay factor is generated until the external clock signal (CLK) reaches the delay line 102 via the clock receiver 101. The second delay factor is generated until data is generated.
Generally, in order to correctly enable the external clock (CLK) to be synchronized with a DQ strobe, the phase of the reference clock signal (refclk) applied to the phase detector 105 must be identical with that of the feedback clock signal (fbclk) applied to the phase detector 105.
The phase detector 105 compares the phase of the reference clock signal (refclk) with that of the feedback clock signal (fbclk), and generates a phase control signal for controlling a delay operation of the delay line 102 according to the comparison result. Therefore, the phase detector 105 maintains synchronization between the feedback clock signal (fbclk) of a feedback path and the reference clock signal (refclk), such that it generates the internal clock signal in which an internal delay component of a DRAM is compensated for the external clock signal.
However, the conventional 4-phase delay locked loop (DLL) uses analog element(s), such that it requires a large amount of power consumption, and has difficulty in guaranteeing operation characteristics at a low voltage, resulting in the occurrence of an unstable locking status.